A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor

Autor:	Vijay Kiran Kalyanam, Eric Mahurin, Keith Bowman, Jacob A. Abraham
Rok vydání:	2020
Předmět:	Digital signal processor Band-pass filter business.industry Computer science Logic gate Clock rate Hardware_INTEGRATEDCIRCUITS Electrical engineering Voltage droop Hardware_PERFORMANCEANDRELIABILITY business Digital signal processing Voltage
Zdroj:	VLSI Circuits
Popis:	A proactive clock-gating system (PCGS) in a 7nm Qualcomm¯ Hexagon™ digital signal processor (DSP) predicts supply voltage (V DD ) droops based on microarchitectural events and a power-delivery-network (PDN) model and adapts clock frequency (F CLK ) to reduce the V DD droop. Silicon measurements demonstrate 10% higher F CLK or 5% lower V DD .
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::b07df89ce1e28a19e4b3343cdc2ef740 https://doi.org/10.1109/vlsicircuits18222.2020.9162808 Zobrazit plný text záznamu