Doubling speed using strained Si/SiGe CMOS technology
| Autor: | L.S. Driscoll, Anthony O'Neill, Douglas J. Paul, Sarah H. Olsen, Sanatan Chattopadhyay, K.S.K. Kwa, Matthew J. Temple |
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| Rok vydání: | 2006 |
| Předmět: |
Materials science
Silicon business.industry Charge carrier mobility Transconductance Metals and Alloys Gate length chemistry.chemical_element Strained silicon Hardware_PERFORMANCEANDRELIABILITY Surfaces and Interfaces Substrate (electronics) Surfaces Coatings and Films Electronic Optical and Magnetic Materials chemistry CMOS MOSFET Hardware_INTEGRATEDCIRCUITS Materials Chemistry Optoelectronics business Hardware_LOGICDESIGN |
| Zdroj: | Thin Solid Films. 508:338-341 |
| ISSN: | 0040-6090 |
| DOI: | 10.1016/j.tsf.2005.07.347 |
| Popis: | The benefit of high performance strained Si CMOS in terms of technology generations is quantified. It is shown that a 0.3 μm gate length strained Si/Si 0.75 Ge 0.25 CMOS technology has the same gate delay as conventional technology having an effective gate length of 0.14 μm, but without the cost of re-tooling. Transconductance enhancements over conventional CMOS in excess of 200% are demonstrated for surface channel n- and p-MOSFETs using a Si 0.75 Ge 0.25 virtual substrate without CMP and a high thermal budget process. To our knowledge these represent the best results reported to date at these dimensions. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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