Analysis and Measurement of Chip Current Imbalance Caused by the Difference of Impedance of Each Parallel Circuit in a Power Module
| Autor: | Takeshi Ohi, Hideo Matsumoto, Hirotaka Muto, Tatsuya Okuda, Toshiyuki Kikunaga |
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| Rok vydání: | 2001 |
| Předmět: |
Engineering
business.industry Busbar Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Insulated-gate bipolar transistor Series and parallel circuits Chip Industrial and Manufacturing Engineering Finite element method Inductance Power module Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business Electrical impedance Hardware_LOGICDESIGN |
| Zdroj: | IEEJ Transactions on Industry Applications. 121:333-339 |
| ISSN: | 1348-8163 0913-6339 |
| DOI: | 10.1541/ieejias.121.333 |
| Popis: | Chip current imbalances caused by the difference of impedance of each parallel circuit in an Insulated Gate Bipolar Transistor (IGBT) module were analyzed using the three dimensional finite element method (3D-FEM). The circuit inductance of the test module was also calculated using the results of the analysis. Measurements of the current of each parallel circuit and circuit inductance using a test module were performed to confirm the results of the analysis. The results of the analysis were in good agreement with the experimental results. The 3D-FEM analysis was therefore used to design a new structure of bus bars in a module and the results presented a good current sharing. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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