Optimal Repeaters for Sub-50nm Interconnect Networks

Autor:	Ajay Joshi, Jeffrey A. Davis, James D. Meindl, Keith Bowman, R. Venkatesan, D.C. Sekar
Rok vydání:	2006
Předmět:	Repeater Combinational logic Engineering business.industry Transistor Electrical engineering Integrated circuit law.invention law Logic gate Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering business AND gate Repeater insertion
Zdroj:	2006 International Interconnect Technology Conference.
DOI:	10.1109/iitc.2006.1648687
Popis:	Power consumed by interconnect repeaters is a serious concern for future ICs. Ways to tackle this issue such as unique optimization of repeater and logic transistor technologies, improved repeater insertion methods and 3D integration are discussed. These techniques reduce total power of a 22 nm 1.4 GHz low power combinational logic block by 55% with negligible performance and area overheads
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::af4ea244d636aa7f8b1d55166b63e3d9 https://doi.org/10.1109/iitc.2006.1648687 Zobrazit plný text záznamu