Dual Si3N4 Charge Trapping Layer (SONNOS) Nonvolatile Memory With Ultra-Thin Body Trench Poly-Si Junctionless FET for 3D NAND Applications

Autor:	Wei-Cheng Wang, Yu-Ru Lin, Yung-Chun Wu, Yi-Wei Chiang
Rok vydání:	2016
Předmět:	Ultra thin body Materials science business.industry Transistor Electrical engineering NAND gate Charge (physics) Trapping law.invention Non-volatile memory law Trench Optoelectronics business Layer (electronics)
Zdroj:	ASME 2016 Conference on Information Storage and Processing Systems.
DOI:	10.1115/isps2016-9541
Popis:	This work presents the structure Junctionless FinFET (JLFinFET) based on ultra-thin body (UTB) with double stacked Si3N4 charge trapping layer (NN-CTL) Si-SiO2-Si3N4-Si3N4-SiO2-Si (SONNOS) nonvolatile memory (NVM). The device shows excellent transistor performances including steep sub-threshold swing (SS) of 76 mV/dec, favorable Vth, and high Ion/Ioff ratio (>107). For n-channel device, it shows excellent memory characteristics, high program/erase (P/E) performance, good endurance (>104 cycles) and an excellent 95∼99% electron retention at 85°C for 10 years.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::af09bd70326df501c84ada080f6d0706 https://doi.org/10.1115/isps2016-9541 Zobrazit plný text záznamu