A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer

Autor:	Terri S. Fiez, Saurabh Saxena, Pavan Kumar Hanumolu, Samira Zali Asl, Kartikeya Mayaram
Rok vydání:	2011
Předmět:	Engineering business.industry Linearity Hardware_PERFORMANCEANDRELIABILITY Chip Delta-sigma modulation Power (physics) Voltage-controlled oscillator CMOS Integrator Low-power electronics Hardware_INTEGRATEDCIRCUITS Electronic engineering business
Zdroj:	CICC
DOI:	10.1109/cicc.2011.6055290
Popis:	A VCO-based MASH delta-sigma ADC architecture is introduced that uses multi-rating of the two stages. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. To demonstrate this architecture, a prototype consisting of a first-order switched-capacitor (SC) integrator with a 4-bit quantizer operating at 100MHz is followed by a second-stage VCO-based ADC operating at 1.2GHz. The chip is implemented in a 130nm 1P8M CMOS process. The measured SNDR is 77dB for a 4MHz signal bandwidth with a power consumption of 13.8mW from a 1.3V supply. The resulting FoM is 298fJ per conversion.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::aef844216301141fb4bf6abcd2f11178 https://doi.org/10.1109/cicc.2011.6055290 Zobrazit plný text záznamu