A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication
| Autor: | Gabriel Pares, Saman Saeedi, Sylvie Menezo, Azita Emami |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Transimpedance amplifier
Engineering Interconnection Silicon photonics business.industry Amplifier 020208 electrical & electronic engineering Electrical engineering Optical communication 02 engineering and technology Atomic and Molecular Physics and Optics law.invention Capacitor 020210 optoelectronics & photonics CMOS law 0202 electrical engineering electronic engineering information engineering Electronic engineering Parasitic extraction business |
| Zdroj: | Journal of Lightwave Technology. 34:2924-2933 |
| ISSN: | 1558-2213 0733-8724 |
| Popis: | Integrating optical receivers based on double-sampling architecture exhibit a low-power alternative to those designed around transimpedance amplifiers (TIA). In this paper, we present a 3D-integrated CMOS/silicon-photonic optical receiver. The receiver features a low-bandwidth TIA integrating front-end double-sampling technique and dynamic offset modulation. The copper-pillar-based 3D-integration technology used here enables ultralow parasitics and 40 μm pitch for interconnection. We study different tradeoffs in designing an optical receiver and how to choose between a full-bandwidth TIA front-end and integrating architecture using a resistive front-end or a low-bandwidth TIA front-end. The design methodology is supported by measurements of two 3D-integrated prototypes based on a conventional TIA and a double-sampling integrating receiver. The proposed receiver architecture achieves −14.9 dBm of sensitivity and energy efficiency of 170 fJ/b at 25 Gb/s, while the conventional receiver achieves a sensitivity of −10.4 dBm and energy efficiency of 260 fJ/b at 21.2 Gb/s. |
| Databáze: | OpenAIRE |
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