| Autor: |
V. Peng, W.J. Bowhill, V.K. Maheshwari, S. Samudrala, P.E. Gronowski, E.M. Copper, B.J. Benschneider, M.N. Gavrielov, J.D. Pickholtz |
| Rok vydání: |
1989 |
| Předmět: |
|
| Zdroj: |
IEEE Journal of Solid-State Circuits. 24:1317-1323 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/jssc.1989.572606 |
| Popis: |
A 135K transistor, uniformly pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor chip is described. The execution unit is capable of sustaining pipelined performance of one 32-bit or 64-bit result every 20 ns for all operations except double-precision multiply (40 ns) and divide. The chip employs an exponent difference prediction scheme and a unified leading-one and sticky-bit computation logic for the addition and subtraction operations. A hardware multiplier using a radix-8 modified Booth algorithm and a divider using a radix-2 SRT algorithm are employed. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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