| Popis: |
A 5 GHz outer-loop phase noise filter (PNF) circuit is proposed to suppress phase noise. By using an active delay line (DL) and sampling circuits to perform the delay-sampling (DS) technique, one can further reduce the phase noise at the selected offset frequency with no need of the reference clock signal. With a 50-ns DL, the PNF circuit achieves 10-dB phase noise reduction at around a 5-MHz offset frequency. This PNF was fabricated in a 40-nm CMOS technology while the core circuit area occupies 0.012 mm2 with 2.97 mW power consumption. |
