Fine resolution delay tuning method to improve the linearity of an unbalanced time‐to‐digital converter on a Xilinx FPGA
| Autor: | Safa Berrima, Yvon Savaria, Yves Blaquiere |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Computer science business.industry 020208 electrical & electronic engineering Linearity 02 engineering and technology Integrated circuit design 01 natural sciences Reduction (complexity) Time-to-digital converter Least significant bit Control and Systems Engineering Command language 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering Routing (electronic design automation) business Field-programmable gate array Computer hardware |
| Zdroj: | IET Circuits, Devices & Systems. 14:1243-1252 |
| ISSN: | 1751-8598 1751-858X |
| DOI: | 10.1049/iet-cds.2020.0026 |
| Popis: | In this study, a method for fine adjustment of Xilinx field programmable gate array (FPGA) routing delays is proposed and applied to improve the linearity of an unbalanced multi-measurement time-to-digital converter (TDC). The delay control method increases load capacitances of interconnect points of switch matrices by small amounts using additional connections to unused interconnects in the FPGA fabric. The novel delay control method uses the tool command language (TCL) scripting feature available in the Xilinx Vivado tool to automatically add wires into a fully placed and routed design. A total of 61 additional wires were successfully and automatically added to reduce the differential and integral non-linearities of the target TDC from 0.51 and −0.54 LSB to 0.05 and 0.06 LSB, respectively (reduction factors of 10.2 and 9) for an LSB equal to 333 ps. |
| Databáze: | OpenAIRE |
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