High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost
| Autor: | Yoshinori Gotoh, Nobutaro Shibata |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Very-large-scale integration
Read-only memory Computer science Sense amplifier business.industry CMOS Application-specific integrated circuit Hardware and Architecture Gate array Logic gate Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering Macro business Software Computer hardware |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:1415-1428 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2014.2341352 |
| Popis: | A gate array has a great advantage in that the extra cost required for customizing VLSI masks is low and the lead time needed to obtain an ASIC is short. Hence, it is widely and generally used in the ASIC industry as a major semicustomized VLSI design methodology. This paper presents high-density RAM/ROM macros using memory-oriented CMOS gate-array base cells. The metatile methodology along with a hierarchical verification technique is used for macro design; all the interconnection wires needed to generate a RAM/ROM macro are installed in each physical leaf cell by way of preparation. The macro size is configurable regarding both word count and bit width. Moreover, back annotations after generating a macro are not necessary because there are no unknown factors such as parasitic resistance and/or capacitance. To reduce the power consumption of RAM/ROM macros, six narrow-channel MOSFETs (two pMOSs and four nMOSs) are prepared in the base cell, resulting in a new 10-transistor-type base cell. Using one single base cell, we can implement an SRAM cell (up to two ports), a 4-bit ROM cell, or a 2-input logic gate. When designing the ROM cell, we adopt a double-rail bitline scheme to shorten the bitline delay. Another high-speed technique is to use a new current-mirror sense amplifier. Owing to the high sensitivity (47 mV) of this amplifier, we have successfully reduced the required read bitline signal from 300 to 100 mVpp. With regards to layout techniques, we propose a new high-density address decoder using a subdecoder and complex logic gates. In addition, some verification techniques using phantom base cells are devised. These techniques are confirmed with a gate-array RAM/ROM macro test chip fabricated with a 0.6- $\mu \text{m}$ low cost, CMOS process. With a two-port SRAM with 256 cells/bitline, the address access time under typical conditions of 3.3 V and 25 °C is 7.125 ns and the power-supply current at a 40-MHz operation is 3.8 mA for an I/O-data width of 1 bit. |
| Databáze: | OpenAIRE |
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