A 0.6 V Resistance-Locked Loop Embedded Digital Low Dropout Regulator in 40 nm CMOS With 80.5% Power Supply Rejection Improvement

Autor:	Chen Chao-Cheng Lee, Chao-Chang Chiu, Ke-Horng Chen, Moris Lin, Tsung-Yen Tsai, Po Hsien Huang, Ying-Hsi Lin
Rok vydání:	2015
Předmět:	Engineering Power supply rejection ratio Low-dropout regulator business.industry Transistor Voltage regulator law.invention CMOS Dropout voltage Duty cycle law MOSFET Electronic engineering Electrical and Electronic Engineering business
Zdroj:	IEEE Transactions on Circuits and Systems I: Regular Papers. 62:59-69
ISSN:	1558-0806 1549-8328
DOI:	10.1109/tcsi.2014.2342380
Popis:	The proposed resistance-locked loop (RLL) can achieve high PSRR of $-$ 16 dB digital low dropout (DLDO) regulator without consuming much power which is the drawback in prior arts. Even at light loads, the RLL can be shut down for power saving. Furthermore, the duty compensator ensures DLDO stability under different duty ratio of supply voltage. The operation voltage of proposed DLDO can be down to 0.6 V and the peak current efficiency is 99.99%. The test chip was fabricated in 40 nm CMOS process with all the transistors implemented by core device for small silicon area.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::aca13d97a83a2f8f1b03155f3a35b6b5 https://doi.org/10.1109/tcsi.2014.2342380 Zobrazit plný text záznamu