Sub-50nm gate length SOI transistor development for high performance microprocessors
| Autor: | D. Greenlaw, Jon D. Cheek, Manfred Horstmann, Christoph Schwan, Markus Lenski, Peter Huebler, Scott Luning, R. van Bentum, N. Kepler, Matthias Schaller, James F. Buller, Hartmut Ruelke, Kai Frohberg, Gert Burbach, Rolf Stephan, J. Klais, S. Krishnan, Jörg Hohage, Andy Wei, Th. Feudel, Michael Raab, G. Grasshoff, Karsten Wieczorek, Martin Gerhardt |
|---|---|
| Rok vydání: | 2004 |
| Předmět: |
Materials science
Silicon business.industry Mechanical Engineering Transistor chemistry.chemical_element Silicon on insulator Nanotechnology Hardware_PERFORMANCEANDRELIABILITY Ring oscillator Condensed Matter Physics Overlayer law.invention chemistry Mechanics of Materials law Gate oxide Shallow trench isolation Hardware_INTEGRATEDCIRCUITS Optoelectronics Inverter General Materials Science business Hardware_LOGICDESIGN |
| Zdroj: | Materials Science and Engineering: B. :3-8 |
| ISSN: | 0921-5107 |
| Popis: | Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|
Full Text from ScienceDirect