The counterflow pipeline processor architecture
| Autor: | Charles E. Molnar, Ivan E. Sutherland, Robert F. Sproull |
|---|---|
| Rok vydání: | 1994 |
| Předmět: |
Reduced instruction set computing
business.industry Computer science Pipeline (computing) Processor design Parallel computing Microarchitecture Pipeline transport Hardware and Architecture Asynchronous communication Embedded system Synchronization (computer science) Electrical and Electronic Engineering business Software Operand forwarding |
| Zdroj: | IEEE Design & Test of Computers. 11:48 |
| ISSN: | 0740-7475 |
| DOI: | 10.1109/mdt.1994.303847 |
| Popis: | The counterflow pipeline processor architecture (CFPP) is a proposal for a family of microarchitectures for RISC processors. The architecture derives its name from its fundamental feature, namely that instructions and results flow in opposite directions within a pipeline and interact as they pass. The architecture seeks geometric regularity in processor chip layout, purely local control to avoid performance limitations of complex global pipeline stall signals, and simplicity that might lead to provably correct processor designs. Moreover, CFPP designs allow asynchronous implementations, in contrast to conventional pipeline designs where the synchronization required for operand forwarding makes asynchronous designs unattractive. This paper presents the CFPP architecture and a proposal for an asynchronous implementation. Detailed performance simulations of a complete processor design are not yet available. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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