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A typical damascene copper plating is a multi-step process, including wafer entry, Cu nucleation, trench filling and thick overburden plating. During these steps, the most important parameters are found to be the entry bias voltage (Evolv), nucleation pulse current (MWE) and the first plating step. It has been observed that a higher bias voltage helps to protect the seed dissolution and therefore improves the slit voids. In addition, an optimized MWE coupled with the first filling current was found to be beneficial to achieve embedded void free plating. This benefit is believed to relate to a thin but uniform Cu nucleation, which provides good conductivity but still leaves enough space in the narrow trenches for Cu to be filled during the first plating step. Fig.1a shows hollow metals signature at 12:00 and 3:00 O’clock position on the post CMP polished wafer surface which were acquired from a defined coordinate of a test macro. However, 1b shows the hollow metals at these locations significantly improved due to the graded plating fill current density in the first few fill steps followed by a potentiostatic entry. In this paper, we will describe how plating recipe could be engineered to minimize plating related defects and improve the overall HOL and reliability for BEOL interconnects. Fig.1(a) API images from the post CMP wafer surface shows hollow metal signature at 12:00 and 3:00 O’clock position. 1(b) shows the hollow metals at these exact same locations significantly improved due to the graded fill current plating. Figure 1 |
