Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers

Autor:	Cheng-Chih Yang, Wing-Kai Hon, Yeong-Jar Chang, Shih-Chieh Chang, Yu-Shih Su
Rok vydání:	2010
Předmět:	Synchronous circuit Computer science Skew Clock skew Computer Graphics and Computer-Aided Design Synchronization Control theory Electronic engineering Algorithm design Minification Electrical and Electronic Engineering Network synthesis filters Software Voltage
Zdroj:	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:1921-1930
ISSN:	1937-4151 0278-0070
DOI:	10.1109/tcad.2010.2061654
Popis:	In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use adjustable delay buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of k ADBs are already determined, we first propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments with a possibility of latency penalty. Then, we propose a modified optimal algorithm without latency penalty. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::aacc4c17fcdfc86e6c1fca7ab082d047 https://doi.org/10.1109/tcad.2010.2061654 Zobrazit plný text záznamu