Design and implementation of the STAR experiment's DAQ
| Autor: | J.M. Nelson, E. Schaefer, M.J. LeVine, A. Ljubicic, R.A. Scheetz, K. Sulimma, M. Nguyen, H. Roehrich, D. Schmischke, J.J. Schambach, M. Botlo, S. Jacobson, F. Heistermann, M.W. Schulz |
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| Rok vydání: | 1998 |
| Předmět: |
Nuclear and High Energy Physics
Engineering business.industry Detector Crate Front and back ends Data acquisition Nuclear Energy and Engineering Application-specific integrated circuit Nuclear electronics Electronic engineering Electrical and Electronic Engineering business Massively parallel Computer hardware VMEbus |
| Zdroj: | IEEE Transactions on Nuclear Science. 45:1907-1912 |
| ISSN: | 1558-1578 0018-9499 |
| Popis: | The STAR experiment is one of the two large detectors currently being built at the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory, Upton, U.S.A. The major issue of STAR's DAQ is the large amount of data that has to be processed as fast as possible. The required data rate is of the order of 90 Gbits/s which has to be processed and scaled down to about 15 MBytes/s and stored to tape or other permanent archiving media. To be able to do so the STAR DAQ uses a custom built ASIC which preprocesses the raw data for later use by a software Level 3 trigger. The Level 3 trigger selects events to be archived depending on physics criteria based upon the particle track information extracted during Level 3 processing. The design presented is a massively parallel multiprocessor system which consists of front end microprocessors hierarchically organized within a VME crate system. Each VME crate contains 6 custom made Receiver Boards with 3 Intel I960HD processors per board for a total of 18 processors per crate. The STAR's TPC detector uses 24 such crates and the SVT detector will use 4 crates for a total of 504 microprocessors. |
| Databáze: | OpenAIRE |
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