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3D integrated circuit (IC) technology can be applied to the already known 2D Network-on-Chip (NoC) approach for System-on-Chips (SoCs). This resulting new approach brings advantages like higher integration density and better performance but also raises the question when the higher implementation costs are really profitable. To answer this question, for a lot of different cases, a framework was developed for simulating 3-dimensional (3D) NoCs, which provides results that are close to real applications and implementations. The framework is highly adaptable in terms of traffic scenarios, available memory, network size (including manual Through-Silicon-VIA (TSV) settings), routing algorithm, chip size and implementation technology. As the complexity of this framework increased in both, environment setup and available information, it was decided to build a graphical user interface (GUI) for an easy access to it. This user interface consists of a lucid configuration interface for generating the traffic scenarios and adjusting all necessary parameters for running a successful simulation. It further provides a front-end for observing the network during the running simulation. To give the user a good notion about the networks behavior, information about the processing elements (PEs) current state, the buffer utilization and the link utilization is displayed in a 2-dimensional (2D) and 3D model of the network. To check if predefined conditions to the energy budget and distributed memory demands are met, an automatically generated post simulation report summarizes all the gained information. This report includes the systems configuration, the buffer fill level, interconnect energy consumption and link utilization for each node and in total. |
