Digital-lithographic processing for thin-film transistor array fabrication
| Autor: | William S. Wong, Robert A. Street, Kateri E. Paul |
|---|---|
| Rok vydání: | 2004 |
| Předmět: |
Amorphous silicon
Electron mobility Materials science business.industry Transistor Condensed Matter Physics Electronic Optical and Magnetic Materials law.invention Threshold voltage chemistry.chemical_compound Semiconductor chemistry law Thin-film transistor Materials Chemistry Ceramics and Composites Optoelectronics Photolithography business Lithography |
| Zdroj: | Journal of Non-Crystalline Solids. :710-714 |
| ISSN: | 0022-3093 |
| DOI: | 10.1016/j.jnoncrysol.2004.03.075 |
| Popis: | Digital lithographic patterning was used to fabricate thin-film transistor devices (TFTs). In one case, hydrogenated amorphous silicon (a-Si:H) TFTs were fabricated using a jet-printed masking method to pattern device features in place of photolithography. Device characteristics were comparable to conventional a-Si:H TFTs with a typical threshold voltage (V T ) of 0.3 V, a carrier mobility (μ) of 0.7 cm 2 /V s, and an on/off ratio of 10 8 . In a second case, solution processable polymeric semiconductors were used to fabricate all print patterned TFTs. These devices had an average V T = -3 V, μ = 0.1 cm 2 /V s, and an on/off ratio of 10 6 . a-Si:H TFT arrays having 64×64 pixels with 300 μm pitch were fabricated using digital lithography. |
| Databáze: | OpenAIRE |
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