High resolution 1280×1024, 15 μm pitch compact InSb IR detector with on-chip ADC

Autor: E. Ilan, R. Gazit, Z. Calalhorra, A. Koifman, Ofer Nesher, I. Vaserman, J. Oiknine Schlesinger, I. Hirsh, I. Pivnik
Rok vydání: 2009
Předmět:
Zdroj: SPIE Proceedings.
ISSN: 0277-786X
DOI: 10.1117/12.817054
Popis: Over the last decade, SCD has developed and manufactured high quality InSb Focal Plane Arrays (FPAs), which are currently used in many applications worldwide. SCD's production line includes many different types of InSb FPA with formats of 320x256, 480x384 and 640x512 elements and with pitch sizes in the range of 15 to 30 μm. All these FPAs are available in various packaging configurations, including fully integrated Detector-Dewar-Cooler Assemblies (DDCA) with either closed-cycle Sterling or open-loop Joule-Thomson coolers. With an increasing need for higher resolution, SCD has recently developed a new large format 2-D InSb detector with 1280x1024 elements and a pixel size of 15μm. The InSb 15μm pixel technology has already been proven at SCD with the "Pelican" detector (640x512 elements), which was introduced at the Orlando conference in 2006. A new signal processor was developed at SCD for use in this mega-pixel detector. This Readout Integrated Circuit (ROIC) is designed for, and manufactured with, 0.18 μm CMOS technology. The migration from 0.5 to 0.18 μm CMOS technology supports SCD's roadmap for the reduction of pixel size and power consumption and is in line with the increasing demand for improved performance and on-chip functionality. Consequently, the new ROIC maintains the same level of performance and functionality with a 15 μm pitch, as exists in our 20 μm-pitch ROICs based on 0.5μm CMOS technology. Similar to Sebastian (SCD ROIC with A/D on chip), this signal processor also includes A/D converters on the chip and demonstrates the same level of performance, but with reduced power consumption. The pixel readout rate has been increased up to 160 MHz in order to support a high frame rate, resulting in 120 Hz operation with a window of 1024×1024 elements at ~130 mW. These A/D converters on chip save the need for using 16 A/D channels on board (in the case of an analog ROIC) which would operate at 10 MHz and consume about 8Watts A Dewar has been designed with a stiffened detector support to withstand harsh environmental conditions with a minimal contribution to the heat load of the detector. The combination of the 0.18μm-based low power CMOS technology for the ROIC and the stiffening of the detector support within the Dewar has enabled the use of the Ricor K508 cryo-cooler (0.5 W). This has created a high-resolution detector in a very compact package. In this paper we present the basic concept of the new detector. We will describe its construction and will present electrical and radiometric characterization results.
Databáze: OpenAIRE