A 2.45-GHz W-level output power CMOS power amplifier with adaptive bias and integrated diode linearizer
| Autor: | Lanqi Liu, Xiaofei Chen, Dongsheng Liu, Xuecheng Zou, Kefeng Zhang, Zhixiong Ren, Zhenglin Liu |
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| Rok vydání: | 2015 |
| Předmět: |
Engineering
Power-added efficiency Adaptive bias business.industry Amplifier RF power amplifier Transistor General Engineering Electrical engineering Biasing Hardware_PERFORMANCEANDRELIABILITY law.invention Linearizer law Hardware_INTEGRATEDCIRCUITS Electronic engineering Power semiconductor device business Hardware_LOGICDESIGN |
| Zdroj: | Microelectronics Journal. 46:327-332 |
| ISSN: | 0026-2692 |
| DOI: | 10.1016/j.mejo.2014.12.009 |
| Popis: | A high-linearity CMOS power amplifier (PA) operating at 2.45GHz for WLAN applications with adaptive bias and an integrated diode linearizer is presented. The PA adopts adaptive bias scheme to adjust the gate bias voltage of power transistors by tracking the output power of the first diver amplifier for efficiency enhancement. Diode-connected MOS transistor is used to compensate the nonlinearity of input capacitance ( C gs ) of power transistors for linearity improvement. The simulation results demonstrate a gain of 33.2dB, a maximum output power of 30.7dBm with 29% of peak power added efficiency (PAE) and -30dBc third-order intermodulation (IMD3) product at 26.4dBm output power, reaching to excellent tradeoffs between efficiency and linearity. |
| Databáze: | OpenAIRE |
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