Hardware reduction for EMB-based Mealy FSM

Autor:	Matgorzata Kolopieńczyk, Marek Wegrzyn, Alexander Barkalov, Larysa Titarenko
Rok vydání:	2015
Předmět:	Set (abstract data type) Reduction (complexity) Control and Systems Engineering Computer science Logic gate RLC circuit Table (database) Parallel computing Field-programmable gate array Algorithm Hardware_LOGICDESIGN Block (data storage)
Zdroj:	IFAC-PapersOnLine. 48:202-207
ISSN:	2405-8963
DOI:	10.1016/j.ifacol.2015.08.132
Popis:	A method is proposed for implementing Mealy FSMs logic circuits with embedded memory blocks. The method is based on encoding of the rows of FSM structure table and replacement of logical conditions. Example of design and results of investigations are given. Our approach allows diminishing the number of LUTs in the block of RLC due to splitting the initial set of logical conditions. Also it results in the decrease of used EMBs for around 15% of standard benchmarks.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::a99f1863f0f6d9914a0beb38bb413916 https://doi.org/10.1016/j.ifacol.2015.08.132 Zobrazit plný text záznamu