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This paper presents a new cost-effective method of designing Single Event Upset (SEU)-tolerant digital systems based on Commercial-Off-The-Shelf (COTS) Field-Programmable-Gate-Array (FPGA) devices. The project was carried out in cooperation of Technical University of Lodz (TUL) with Deutsches Elektronen-Synchrotron (DESY). DESY is a high-energy particle physics research centre, located in Hamburg, Germany, and has been chosen as a home site for a new generation particle collider - X-Ray Free Electron Laser (X-FEL) accelerator. A need of implementing digital control systems inside accelerators main tunnel, brought a new hardware approach to low-cost design reliable compex circuits with respect to Single Event Effects (SEEs). The goal was to develop a high performance method without modifications in the FPGA architecture and without high area penalties. A SEU-tolerant, digital library has been created. From basic gates, through combinational and sequential cells to some more sophisticated units like memory blocks, code converters or arithmetical functions cells, in all elements upset detection and mitigation schemes have been implemented. The library was described in Very High Speed Integrated Circuit Hardware Description Language (VHDL). |
