Formal Verification of Signalling Programs with SafeCap
| Autor: | Dominic Taylor, Linas Laibinis, Alexei Iliasov, Alexander Romanovsky |
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| Rok vydání: | 2018 |
| Předmět: |
Focus (computing)
business.industry Computer science 020207 software engineering 02 engineering and technology Signalling Work (electrical) Software deployment Scalability Railway signalling 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Software engineering business Formal verification Interlocking |
| Zdroj: | Developments in Language Theory ISBN: 9783319986531 SAFECOMP |
| DOI: | 10.1007/978-3-319-99130-6_7 |
| Popis: | SafeCap is a modern toolkit for modelling, simulation and formal verification of railway networks. This paper discusses the use of SafeCap for formal analysis and fully-automated scalable safety verification of solid state interlocking (SSI) programs – a technology at the heart of many railway signalling solutions. The focus of the work is on making it easy for signalling engineers to use the developed technology and thus to help with its smooth industrial deployment. In this paper we explain the formal foundations of the proposed method, its tool support, and their application to real life railway verification problems. |
| Databáze: | OpenAIRE |
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