| Autor: |
Dileep Dwivedi, Antriksh Sharma |
| Rok vydání: |
2019 |
| Předmět: |
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| Zdroj: |
Lecture Notes in Electrical Engineering ISBN: 9789811367717 |
| DOI: |
10.1007/978-981-13-6772-4_63 |
| Popis: |
This paper presents a comparative study between the conventional CMOS technique and the MOS current mode logic. The basic inverter logic gate designed by both the styles has been analyzed by varying the power supply voltage as well as the frequency of operation. Power dissipation and delay generated by both the circuits have been investigated. A close inspection reveals that MCML technique proves to be far more superior to the currently existing CMOS style at higher frequencies of operation as its power dissipation is minimal when compared with CMOS. Results show that at high frequencies such as 9 GHz, the dissipation of power by MCML inverter is only 5.54 µW as compared to a much higher value of 13.612 µW that is dissipated by CMOS inverter. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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