Architecture and methodology of a SoPC with 3.25Gbps CDR based SERDES and 1Gbps dynamic phase alignment

Autor:	Tin H. Lai, Arch Zaliznyak, Chong Lee, Kazi Asaduzzaman, John Lam, Shoujun Wang, Binh Ton, Wilson Wong, Victor Maruri, Simardeep Maangat, Henry Y. Lui, Huy Ngo, Tim Tri Hoang, Ramanand Venkata, Tam Nguyen, Mei Luo, Tung Hoang Tran, Toan Nguyen, Malik Kabani, Rakesh H. Patel, Vinson Chan, S. Shumurayev
Rok vydání:	2004
Předmět:	Engineering business.industry SerDes Chip Programmable logic array Logic synthesis Embedded system Stratix Hardware_INTEGRATEDCIRCUITS System on a chip Transceiver business Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION Hardware_LOGICDESIGN
Zdroj:	CICC
DOI:	10.1109/cicc.2003.1249481
Popis:	The SoPC (system on a programmable chip) aspects of the Stratix GX/spl trade/ FPGA with 3.125 Gbps SERDES are described. The FPGA was fabricated on a 0.13 /spl mu/m, 9-layer metal process. The 16 high-speed serial transceiver channels with clock data recovery (CDR) provides 622-Megabits per second (Mbps) to 3.125-Gbps full-duplex transceiver operation per channel. Another challenge described is the implementation of 39 source-synchronous channels at 100 Mbps to 1 Gbps, utilizing dynamic phase alignment (DPA). The implementation and integration of the FPGA logic array (with its own hard IP) with the CDR and DPA channels involved grappling with SoC design issues and methodologies.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::a9082146443f2f3ba9afbe73a75d6bc6 https://doi.org/10.1109/cicc.2003.1249481 Zobrazit plný text záznamu