Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling

Autor:	Franklin M. Baez, K.T. Tang, Dimitrios Velenis, Eby G. Friedman, I.S. Kourtev, V. Adler
Rok vydání:	2002
Předmět:	Synchronous circuit business.industry Clock signal Computer science Embedded system Clock rate Static timing analysis Digital clock manager business Clock skew Computer hardware Timing failure CPU multiplier
Zdroj:	ICECS
DOI:	10.1109/icecs.2001.957650
Popis:	A demonstration of the application of non-zero clock skew scheduling to enhance the speed characteristics of several functional unit blocks in a high performance processor is presented. It is shown that non-zero clock skew scheduling can improve circuit performance while relaxing the strict timing constraints of the critical data paths within a high speed system. A software tool implementing a non-zero clock skew scheduling algorithm is described together with a methodology that generates the required clock signal delays by replacing clock buffers from predesigned cell libraries. Timing margin improvements of up to 18% are achieved through the application of non-zero clock skew scheduling in certain functional blocks of an industrial high performance microprocessor.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::a8e8e1b1c27cdd52ce1e8e327c33b3d0 https://doi.org/10.1109/icecs.2001.957650 Zobrazit plný text záznamu