19.6 A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode
| Autor: | Francois Stas, Pengcheng Xu, David Bol, Denis Flandre, Maxime Schramme, Thomas Haine, Charlotte Frenkel, Remi Dekimpe, Ludovic Moreau |
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| Rok vydání: | 2019 |
| Předmět: |
Computer science
business.industry Dual loop Electrical engineering 02 engineering and technology AC power 020202 computer hardware & architecture Power (physics) Generator (circuit theory) Microcontroller Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering business Sleep mode Electronic circuit Voltage |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2019.8662293 |
| Popis: | Near-threshold circuits operating at ultra-low voltage (ULV) have matured with integration in commercial products, such as ultra-low-power (ULP) MCUs for the IoT [1]. In this market, MCU design faces the key performance tradeoff between speed, active power, deep-sleep retention power and wakeup time, with the challenge of preserving it over PVT corners. We present a ULP MCU SoC in 28nm FDSOI codenamed SleepRunner, exploiting back-biasing (BB) capability of FDSOI to push the performance tradeoff beyond the state-of-the-art. |
| Databáze: | OpenAIRE |
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