Test generation for sequential circuits using parallel fault simulation with random inputs
| Autor: | Isao Higashi, Tsuyoshi Kodama, Yuzo Takamatsu |
|---|---|
| Rok vydání: | 1995 |
| Předmět: |
Sequential logic
Computer science CPU time Parallel computing Test method Automatic test pattern generation Fault (power engineering) Theoretical Computer Science Computational Theory and Mathematics Hardware and Architecture Benchmark (computing) Code generation State (computer science) Algorithm Information Systems |
| Zdroj: | Systems and Computers in Japan. 26:24-34 |
| ISSN: | 1520-684X 0882-1666 |
| Popis: | This paper presents a simple test generation method for sequential circuits using a parallel simulator with random inputs. The proposed test generation method generates sequences by simulating as many states as possible, without using a cost function for a target fault. To generate effective test sequences, dynamic switching is done between I-Mode and S-Mode parallel simulators. Here the I-Mode simulates 32 patterns for one state in parallel and the S-Mode simulates 32 patterns for 32 states in parallel. Experimental results for ISCAS'89 benchmark sequential circuits show that our method achieves test sequences with high coverage in acceptable CPU time. |
| Databáze: | OpenAIRE |
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