C-CREST Technique for Combinational Logic SET Testing
| Autor: | M.C. Casey, Bharat L. Bhuva, J. R. Ahlbin, Michael W. McCurdy, A. Balasubramanian, O.A. Amusan, Dolores A. Black, Jeffrey D. Black, Robert A. Reed, Lloyd W. Massengill |
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| Rok vydání: | 2008 |
| Předmět: |
Digital electronics
Combinational logic Nuclear and High Energy Physics Engineering Sequential logic business.industry Logic family Programmable logic array Programmable logic device Nuclear Energy and Engineering Electronic engineering Electrical and Electronic Engineering business Hardware_LOGICDESIGN Logic optimization Register-transfer level |
| Zdroj: | IEEE Transactions on Nuclear Science. 55:3347-3351 |
| ISSN: | 0018-9499 |
| DOI: | 10.1109/tns.2008.2005900 |
| Popis: | SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the combinational circuit for radiation effects self-test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM's 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty. |
| Databáze: | OpenAIRE |
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