Adaptive Low-Pass Filter Based DC Offset Removal Technique for Three-Phase PLLs
| Autor: | Parag Kanjiya, Mohamed Shawky El Moursi, Vinod Khadkikar |
|---|---|
| Rok vydání: | 2018 |
| Předmět: |
Computer science
020209 energy Low-pass filter 020208 electrical & electronic engineering Bandwidth (signal processing) Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology Filter (signal processing) Fundamental frequency Cutoff frequency Phase-locked loop Three-phase Control and Systems Engineering Control theory Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electrical and Electronic Engineering DC bias |
| Zdroj: | IEEE Transactions on Industrial Electronics. 65:9025-9029 |
| ISSN: | 1557-9948 0278-0046 |
| DOI: | 10.1109/tie.2018.2814015 |
| Popis: | The presence of dc offset in the inputs of a phase-locked loop (PLL) introduces fundamental frequency oscillations in the estimated quantities. Due to their low frequency in a synchronous reference frame, removal of these oscillations is a challenging task. Recent design studies of pre/in-loop filtering based advanced PLLs show that incorporation of dc offset removal in a filtering stage reduces the bandwidth of the PLL. This degrades the dynamic performance of the PLL and results in slower response time. To tackle this issue, a simple yet effective dc offset removal technique based on adaptive low-pass filters is introduced in this letter. The proposed technique can be applied as an add-on to any PLL structures without altering their design. Therefore, its application has a minimal effect on the dynamic performance of the PLL under study. The effectiveness of the proposed technique is evaluated experimentally by applying it to different PLL structures. |
| Databáze: | OpenAIRE |
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