Bist for deep submicron asic memories with high performance application

Autor:	J. Rayhawk, O. Samman, Wu-Tung Cheng, Theo J. Powell, S. Lai, P. Policke
Rok vydání:	2004
Předmět:	Read-write memory Application-specific integrated circuit business.industry Sense amplifier Computer science Embedded system Interleaved memory Registered memory Semiconductor memory Memory refresh business Computer hardware Computer memory
Zdroj:	ITC
Popis:	Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tight layouts. These two trends are putting much greater demands upon memory BIST requirements. At-speed testing and custom test algorithms are becoming essential for insuring overall product quality. At-speed testing on memories that now operate in the 10 to 800 MHz range can be a challenge. Another demand upon memory BIST is determining the location of defects so that the cause can be diagnosed, or repaired with redundant cells. A tool and methodology that meets these difficult requirements is discussed.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::a6d0d397dc03eacbf39833e2613b6f96 https://doi.org/10.1109/test.2003.1270862 Zobrazit plný text záznamu