High-Level Synthesis-Based Approach for Accelerating Scientific Codes on FPGAs
| Autor: | Anne C. Elster, Ashish Misra, Volodymyr Kindratenko, Ramshankar Venkatakrishnan |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
General Computer Science
Point (typography) Computer science business.industry 05 social sciences General Engineering 050301 education Design elements and principles Software High-level synthesis Embedded system 0501 psychology and cognitive sciences business Field-programmable gate array Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION 0503 education Hardware_LOGICDESIGN 050104 developmental & child psychology |
| Zdroj: | Computing in Science & Engineering. 22:104-109 |
| ISSN: | 1558-366X 1521-9615 |
| DOI: | 10.1109/mcse.2020.2996072 |
| Popis: | High-level synthesis (HLS) and OpenCL are the two leading high-level design platforms that are becoming widely used for programming FPGAs. Their proponents claim that these tools require little to no knowledge of the hardware design principles and can significantly improve developer's productivity. In this article, the author explore these two high-level design approaches from the point of view of a software developer. The author use Xilinx Vivado HLS C/C++ ver. 2019.1 and Xilinx SDAccel OpenCL ver. 2019.1 to implement a cross -correlation operation from scratch and synthesize it for a Xilinx u250 Alveo FPGA board. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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