| Autor: |
M.H. Taufique, Bo Jiang, Belliappa Kuttanna, M. D'Addeo, F. Merchant, Binta M. Patel, H. Samarchi, S. Curtis, G. Gerosa |
| Rok vydání: |
2008 |
| Předmět: |
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| Zdroj: |
2008 IEEE Asian Solid-State Circuits Conference. |
| Popis: |
This paper describes a low power Intelreg Architecture (IA) processor specifically designed for mobile internet devices (MID). The design consists of an in-order pipeline capable of issuing 2 instructions per cycle supporting 2 threads, 32 KB instruction and 24 KB data L1 caches, independent integer and floating point execution units, a 512 KB L2 cache and a 533 MT/s dual-mode (GTL and CMOS) front-side-bus (FSB). The design contains 47 million transistors in a die size under 25 mm2 manufactured in a 9-metal 45 nm CMOS process. Thermal design power (TDP) consumption is measured at 2 W, 1.0 V, 90degC using a synthetic power-virus test at a frequency of 1.86 GHz. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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