A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET
| Autor: | David Mahashin, Tim Cronin, Adebabay M. Bekele, Stanley Chen, Hongyuan Zhao, Ian Zhuang, Parag Upadhyaya, Adam Chou, Winson Lin, Kee Hian Tan, Dave Freitas, Lei Zhou, Kok Lim Chan, Yohan Frans, Jay Im, Ken Chang, Didem Turker |
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| Rok vydání: | 2018 |
| Předmět: |
Very-large-scale integration
Computer science Wireline Lock time 020208 electrical & electronic engineering Detector Transmitter 02 engineering and technology law.invention Programmable-gain amplifier law 0202 electrical engineering electronic engineering information engineering Electronic engineering Transceiver Transformer |
| Zdroj: | VLSI Circuits |
| DOI: | 10.1109/vlsic.2018.8502275 |
| Popis: | A 28Gb/s NRZ wireline transceiver is implemented in 7nm FinFET. A transformer-based LC-PLL sends a single-phase differential clock to the voltage-mode transmitter and the receiver. Local multi-phase clocks are generated in each TX/RX lane to support digital phase interpolation. The receiver equalization consists of a single-stage CTLE that performs both high-frequency peaking and long-tail cancellation, a two-stage programmable gain amplifier, and a 15-tap DFE. The digital CDR achieves |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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