Efficient Generation of Compact Execution Traces for Multicore Architectural Simulations
| Autor: | Muhammad Elnasir Elrabaa, Ayman Hroub, Muhamed F. Mudawar, Ahmad Khayyat |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Multi-core processor Computer science media_common.quotation_subject Suite Fidelity Binary number 02 engineering and technology Parallel computing 01 natural sciences Functional simulation 020202 computer hardware & architecture Hardware and Architecture 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Threading (manufacturing) Trace compression Software Information Systems media_common |
| Zdroj: | ACM Transactions on Architecture and Code Optimization. 14:1-25 |
| ISSN: | 1544-3973 1544-3566 |
| DOI: | 10.1145/3106342 |
| Popis: | Requiring no functional simulation, trace-driven simulation has the potential of achieving faster simulation speeds than execution-driven simulation of multicore architectures. An efficient, on-the-fly, high-fidelity trace generation method for multithreaded applications is reported. The generated trace is encoded in an instruction-like binary format that can be directly “interpreted” by a timing simulator to simulate a general load/store or x8-like architecture. A complete tool suite that has been developed and used for evaluation of the proposed method showed that it produces smaller traces over existing trace compression methods while retaining good fidelity including all threading- and synchronization-related events. |
| Databáze: | OpenAIRE |
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