Area-efficient 3-input decimal adders using simplified carry and sum vectors
| Autor: | Hsin-Hao Peng, Chao-Tsung Kuo, Tso-Bing Juang |
|---|---|
| Rok vydání: | 2011 |
| Předmět: |
Very-large-scale integration
Adder Computer science Computation Carry (arithmetic) Decimal floating point MathematicsofComputing_NUMERICALANALYSIS Data_CODINGANDINFORMATIONTHEORY Operand Binary Integer Decimal Decimal ComputingMethodologies_SYMBOLICANDALGEBRAICMANIPULATION Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic Hardware_LOGICDESIGN |
| Zdroj: | VLSI-SoC |
| DOI: | 10.1109/vlsisoc.2011.6081625 |
| Popis: | In this paper, we have proposed area-efficient 3-input decimal adders using simplified carry and sum vectors. By using proposed generator circuits and the recursive generation of correction terms, our proposed decimal adders could perform efficient summations with three inputs of operands. Synthesis shows that our proposed adders save up to 39.2 % area cost compared to previous reported decimal adders with three inputs under the same delay constraint. The proposed adders could be easily modified to perform 4-input decimal additions. Besides that, the power consumptions for our decimal adders are at most 50% lesser. Our proposed decimal adders could be applied to ease the tremendous computation efforts for decimal numbers. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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