Implementation of MELP Encoder on Zynq FPGA using HLS

Autor: M Koushik, D. Saravanan, Jyoti Yadav, Jawed Qumar, Shashidhar Shivanagi
Rok vydání: 2017
Předmět:
Zdroj: 2017 International Conference on Current Trends in Computer, Electrical, Electronics and Communication (CTCEEC).
DOI: 10.1109/ctceec.2017.8455186
Popis: For the speech communication techniques there is a lot of scope nowadays. Due to number of applications increasing, there is a need for the approach for the data compression techniques which uses bandwidth and storage space. The quality of original speech is maintained for the speech coding techniques which reduces the bit rates. The Multi-Excitation Linear Prediction (MELP)[1,3] speech coder is the Federal Standard which provides a good quality of the decoded speech. The MELP Encoder is implemented through HLS on to the Zynq-7 ZC706 FPGA Evaluation Board. The comparison of the area utilization is done at C-synthesis level, post-synthesis level, post- implementation level.
Databáze: OpenAIRE