| Autor: |
Yu-Syuan Lin, Chih-Yuan Chan, Hong-Yu Lin, Shawn S. H. Hsu, Jun-De Jin |
| Rok vydání: |
2007 |
| Předmět: |
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| Zdroj: |
IEEE Transactions on Circuits and Systems II: Express Briefs. 54:750-754 |
| ISSN: |
1057-7130 |
| DOI: |
10.1109/tcsii.2007.901258 |
| Popis: |
A fully integrated frequency divider with an operation frequency up to 20 GHz is designed in 0.18-mum CMOS technology. The frequency divider includes two stages to divide the input signal by a factor of 4. A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase noise of -134.8 dBc/Hz (1-MHz offset) at an output frequency of 4.7 GHz. The first stage is designed by an analog methodology with the varactors to extend the locking range, while the second stage is designed by a digital approach with the RF devices for a high operation frequency. With the advantages of both designs, this frequency divider is operated at the frequency range suitable for LMDS applications. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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