Reliability and Performance of CMOS-Compatible Multi-Level Graphene Interconnects Incorporating Vias
| Autor: | Junkai Jiang, Kaustav Banerjee, Chao-Hui Yeh, Kamyar Parto, Kunjesh Agashiwala, Dujiao Zhang |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010302 applied physics
Materials science Yield (engineering) Graphene business.industry Contact resistance Dielectric 01 natural sciences Electromigration law.invention Reliability (semiconductor) law Electrical resistivity and conductivity 0103 physical sciences Optoelectronics business Cmos compatible |
| Zdroj: | 2020 IEEE International Electron Devices Meeting (IEDM). |
| Popis: | Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects for extremely scaled dimensions [1],[2]. Even though single-level scaled graphene wires have been demonstrated with comparable or lower resistivity and higher reliability w.r.t dual-damascene (DD) and SE-enabled metal-wires [1]-[3], the reliability and performance of a multi-level graphene interconnect technology (with vias) have remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on both dielectric (SiO 2 ) and metallic (Cu) substrates, and subsequently demonstrating SE-enabled multilevel MLG-interconnects with edge-contacting metal-vias. Electrical and reliability characterizations establish that |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|