Impact of Fin Line Edge Roughness and Metal Gate Granularity on Variability of 10-nm Node SOI n-FinFET
| Autor: | Akhil Sudarsanan, Sankatali Venkateswarlu, Kaushik Nayak |
|---|---|
| Rok vydání: | 2019 |
| Předmět: |
010302 applied physics
Physics Silicon on insulator Short-channel effect 01 natural sciences Electronic Optical and Magnetic Materials Fin (extended surface) Computational physics Threshold voltage Logic gate 0103 physical sciences Granularity Electrical and Electronic Engineering Diffusion (business) Metal gate |
| Zdroj: | IEEE Transactions on Electron Devices. 66:4646-4652 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2019.2941896 |
| Popis: | We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work function variability induced by metal gate granularity (MGG) and Fin line edge roughness (LER) using quantum corrected 3-D drift diffusion (DD) simulation framework. The statistical simulation predictions reveal that for ultra downscaled SOI FinFET, the MGG predominantly affects device threshold voltage. Similarly, the LER sources are found to strongly influence the variability of device short channel effect immunity and channel mobility of carriers. Both MGG and long correlation length LER are found to strongly influence the overlap and outer fringing parasitic capacitances variability, resulting in increased variability of device intrinsic speed. It is predicted that the presence of combined random fluctuation sources results in the increased variability of threshold mismatch index ( $A_{\text {VT}}$ ) for the sub-10-nm SOI FinFET technology. |
| Databáze: | OpenAIRE |
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