Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor
| Autor: | I. Parulkar, Peter F. Lai, Georgios Konstadinidis, Yuefei Ge, S. Parampalli, Marc Tremblay, Ilyas Elkin, Mamun Rashid, Y. Otaguro, Shailender Chaudhry, Leonard D. Rarick, Rambabu Pyapali, Y. Orginos, S. Gundala, M. Steigerwald |
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| Rok vydání: | 2009 |
| Předmět: |
Multi-core processor
Out-of-order execution business.industry Computer science Register file Hardware scout Transactional memory Hardware_PERFORMANCEANDRELIABILITY Thread (computing) law.invention Microprocessor Shared memory Shared memory architecture law Multithreading Embedded system Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering business |
| Zdroj: | IEEE Journal of Solid-State Circuits. 44:7-17 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/jssc.2008.2007144 |
| Popis: | This third-generation Chip-Multithreading (CMT) SPARC processor consists of 16 cores with shared memory architecture and supports a total of 32 main threads plus 32 scout threads. It is targeted for high-performance servers, and is optimized for both single- and multi-threaded applications. The 396 mm2 chip is fabricated in an 11 metal layer 65-nm CMOS process and operates at a nominal frequency of 2.3 GHz, consuming a maximum power of 250 W at 1.2 V. This paper provides an overview of the architectural highlights and describes the physical implementation challenges and solutions including circuit innovations in memory arrays, register files, and floating-point hardware that boost the performance and circuit robustness with low area overhead. |
| Databáze: | OpenAIRE |
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