Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology
| Autor: | Rui Liu, Rick Wong, Bharat L. Bhuva, M. Newton, L. Chen, R. Fung, Sanghyeon Baeg, S.-J. Wen, Yuanqing Li, Mo Chen, N. N. Mahatme, K. Lilja, Haibin Wang |
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| Rok vydání: | 2016 |
| Předmět: |
Physics
Nuclear and High Energy Physics Synchronous circuit 010308 nuclear & particles physics Clock signal 020208 electrical & electronic engineering Clock gating 02 engineering and technology Digital clock manager Topology Clock skew 01 natural sciences Timing failure Nuclear Energy and Engineering Clock domain crossing 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Electronic engineering Electrical and Electronic Engineering CPU multiplier |
| Zdroj: | IEEE Transactions on Nuclear Science. 63:385-391 |
| ISSN: | 1558-1578 0018-9499 |
| DOI: | 10.1109/tns.2015.2509443 |
| Popis: | Two types of clock networks including clock mesh and a buffered clock tree in a daisy-chain style were utilized to synchronize 5 DFF chains and fabricated in a 28 nm bulk CMOS technology. Alpha and proton particles did not trigger any errors indicating the significant single event tolerance of these clock networks. Heavy ion results for the data input pattern of checkerboard (alternate 1 and 0) are presented showing few occurrences of burst errors induced by single event transients (SETs) in the buffered clock tree at relatively high LET values. The same phenomena were observed in laser tests. Clock mesh is therefore proven to be less sensitive to SETs, if pre-mesh drivers do not generate transients. Otherwise, clock mesh possesses lower tolerance, as demonstrated in previous work. Moreover, these burst errors occurred (1) simultaneously in a DFF chain and its subsequent chains, or (2) in a single chain with subsequent chains unaffected. The distinct mechanisms of these burst errors were found to be the electrical masking effect of the daisy-chain clock buffers. |
| Databáze: | OpenAIRE |
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