| Autor: |
R. Mundhada, Vijayavardhan Baireddy, Himamshu Gopalakrishna Khasnis |
| Rok vydání: |
2007 |
| Předmět: |
|
| Zdroj: |
2007 International Symposium on Signals, Systems and Electronics. |
| DOI: |
10.1109/issse.2007.4294498 |
| Popis: |
A programmable 64-4096 point FFT/ IFFT/Windowing processor for DSL applications is discussed. Dynamic scaling, computation restructuring in terms of radix-2 butterfly and clustered computation power down methods are presented. The single multiplier based 360 MHz design occupies 0.38 sqmm of area in 90 nm process and consumes 19.8 mW of dynamic power for a 4096 point computation. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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