Highly Manufacturable Single Metal Gate Process Using Ultra-Thin Metal Inserted Poly-Si Stack (UT-MIPS)

Autor:	Cheol-kyu Lee, Min-Joo Kim, Jong-Ho Lee, Hyung-Suk Jung, Young-Sub You, Young Su Chung, Ho-Kyu Kang, Hionsuck Baik, Hajin Lim, Sung Kee Han, Mong sub Lee, Nae In Lee, Eunha Lee
Rok vydání:	2006
Předmět:	Materials science Silicon business.industry chemistry.chemical_element Nanotechnology PMOS logic Atomic layer deposition Stack (abstract data type) chemistry MOSFET Optoelectronics Metal gate business NMOS logic Voltage
Zdroj:	2006 International Electron Devices Meeting.
DOI:	10.1109/iedm.2006.346860
Popis:	The authors have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are carefully examined, and then the other parameters are optimized to give the best performance. As a results, low and symmetrical short channel Vth (0.44/-0.48 V for n/pMOS) and excellent drive currents (620/230 muA/mum for n/pMOS at Ioff =20pA/mum and Vdd=1.2 V) are obtained without using any mobility enhancement strain technology. The estimated operation voltage for 10 years lifetime of optimized UT-MIPS devices (1.25 V for nMOS PBTI and 1.5 V pMOS NBTI) are well beyond the 1.2 V, showing the good reliability characteristics of UT-MIPS devices as well
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::a2b4619b61ccca2ba78077b45f374fbb https://doi.org/10.1109/iedm.2006.346860 Zobrazit plný text záznamu