Reliability Analysis of Reconfiguration Controller for FPGA–Based Fault Tolerant Systems: Case Study
| Autor: | Richard Panek, Zdenek Kotasek, Jakub Lojda, Jakub Podivinsky |
|---|---|
| Rok vydání: | 2020 |
| Předmět: |
010308 nuclear & particles physics
business.industry Computer science Reliability (computer networking) Control reconfiguration Fault tolerance 02 engineering and technology 01 natural sciences Reduction (complexity) Control theory 020204 information systems Embedded system Control system 0103 physical sciences Lookup table 0202 electrical engineering electronic engineering information engineering Hardware_ARITHMETICANDLOGICSTRUCTURES Field-programmable gate array business |
| Zdroj: | VLSI-DAT |
| DOI: | 10.1109/vlsi-dat49148.2020.9196269 |
| Popis: | This paper deals with a reliability analysis of a reconfiguration controller which can be a component of a faulttolerant control system. This controller is designed for an FPGA to be capable of using partial dynamic reconfiguration of the FPGA to mitigate potential faults in the FPGA’s configuration memory. These faults, which are called SEUs, can be induced by radiation effects. Therefore, fault tolerance measurement or estimation is very important for designing circuits for critical environments. Thus, the reliability of the reconfiguration controller itself is significant; therefore the Fault Tolerance ESTimation (FT-EST) framework is used for reliability evaluation, which is procured by the discovery of a number of critical configuration bits. Two approaches are used and compared: evaluations of used LUT only, and evaluations of all configuration bits. We ascertained a 20x reduction in time consumption at the expense of a proportional decrease in the amount of critical configuration bits discovered. The obtained results are nearly equivalent. |
| Databáze: | OpenAIRE |
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