Low temperature endurance failures on flash memory
| Autor: | Stephen Heinrich-Barna, Doug Verret, C.F. Dunn |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Engineering business.industry Transistor 0211 other engineering and technologies Electrical engineering 02 engineering and technology 01 natural sciences Flash memory Signature (logic) law.invention Flash (photography) Reliability (semiconductor) Depletion region law Logic gate 021105 building & construction 0103 physical sciences Hardware_INTEGRATEDCIRCUITS business NMOS logic |
| Zdroj: | ISQED |
| DOI: | 10.1109/isqed.2017.7918298 |
| Popis: | Write-erase cycling of flash memories has distinct failure signatures that have been thoroughly documented in the literature. A new mechanism has been uncovered when cycling at low temperatures. On the 65nm embedded flash technology, units exhibited a programming failure signature. However, further investigation verified that fail bits were fully programmed. Cause of failure was attributed to a non-classical hot carrier mechanism affecting an NMOS transistor in the sense circuitry. This was not expected as the Vds of the affected transistor was relatively low. TCAD simulations verified that the back bias on the transistor heated up electrons in the drain space charge region, generating secondary electrons from avalanche multiplication. The details of the failure mechanism, previously unpublished and unknown to current reliability tools, will be discussed and the corrective actions will be identified. |
| Databáze: | OpenAIRE |
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