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This paper presents a timing analysis tool for CMOS integrated circuits: TVA. The algorithm is organized around a breadth-first critical path analysis technique, which dynamically partitions data paths in unidirectional macros, including transmission gate arrays and driving inverters, and calculates the worst case delays by using closed form equations taking into account load conditions and driving waveform. With SPICE compatible input file, this predictor provides an excellent speed-accuracy trade-off. |
