Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

Autor:	S. Kanda, S. Yamaguchi, K. Tanaka, Hitoshi Wakabayashi, R. Yamamoto, Hayato Iwamoto, T. Hirano, J. Wang, Yuki Miyanami, K. Kugimiya, Itaru Oshiyama, Yoshihiko Nagahama, K. Ogawa, Y. Tagawa, Naoki Nagashima, Shinya Yamakawa, Masaki Saito, Masashi Nakata, Satoru Mayuzumi, Yoshiya Hagimoto, Y. Tateshita, Masanori Tsukamoto, Shingo Kadomura, Kaori Tai, K. Nagano, Y. Yamamoto
Rok vydání:	2007
Předmět:	Electron mobility Materials science business.industry Gate stack Copper interconnect Stress (mechanics) Metal visual_art MOSFET Electronic engineering visual_art.visual_art_medium Optoelectronics Work function business High-κ dielectric
Zdroj:	2007 IEEE International Electron Devices Meeting.
DOI:	10.1109/iedm.2007.4418926
Popis:	Extreme high-performance n- and pFETs are achieved as 1300 and 1000 uA/um at Ioff = 100 nA/um and Vdd = 1.0 V, respectively, by applying newly proposed booster technologies. The combination of top-cut dual-stress liners and damascene gate remarkably enhances channel stress especially for shorter gate lengths. High-Ion pFETs with compressive stress liners and embedded SiGe source/drain are performed by using ALD-TiN/HfO2 damascene gate stacks with Tinv = 1.4 nm on (100) substrates. On the other hand, nFETs with tensile stress liners are obtained by using HfSix/HfO2 damascene gate stacks with Tinv =1.4 nm.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::a206c5da2929f135c3396319b66fa27e https://doi.org/10.1109/iedm.2007.4418926 Zobrazit plný text záznamu