Design of Low Power Bypassing-Based Multiplier Using Vhdl

Autor:	Mamta Mahajan, Anupa. S. Kavale, Dinesh Rotake
Rok vydání:	2014
Předmět:	Computer science VHDL Multiplier (economics) Hardware_ARITHMETICANDLOGICSTRUCTURES Arithmetic computer Parallel array AND gate NOR gate computer.programming_language
Zdroj:	IOSR Journal of Electronics and Communication Engineering. 9:77-81
ISSN:	2278-2834 2278-8735
DOI:	10.9790/2834-09337781
Popis:	In this paper a low power bypassing -based multiplier design is present, in which reduction in power is to be achieved in changed partial products of column bypassing multiplier as compared to column bypassing multiplier by exchange NOR gates with AND gates in the conventional multiplier I.e. in the design of conventional multiplier rather than AND gate, NOR gate is employed victimization DeMorgan’s theorem. Compare with 32×32 bits typical (parallel array) multiplier and column bypassing multiplier, this planned system reduces power.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::a201d92543112a68424169f5cfbbe8a7 https://doi.org/10.9790/2834-09337781 Zobrazit plný text záznamu